Ephrem Wu is a Senior Director in Silicon Architecture at Xilinx. His current focus is neural-net accelerators. Since joining Xilinx in 2010, Ephrem led the definition of UltraRAM in the UltraScale+ family and spearheaded the design of the first 2.5D-stacked FPGA with 28 Gb/s serdes.

From 2000-2010, Ephrem led backplane switch and security processor development at Velio Communications and LSI. Prior to Velio, he developed hardware and software at SGI, HP, Panasonic, and AT&T. Ephrem holds 27 U.S. patents. He earned a bachelor's degree from Princeton University and a master's degree from the University of California, Berkeley, both in EE.

Unlocking Latent Performance

Reconfigurable numerical solutions often leave performance on the table.For instance, a 20nm FPGA DSP resource has a maximum clock frequency (Fmax) of 661MHz, but designs built from an array of DSPs typically operate between 200 to 300MHz, achieving only a third to a half of the potential throughput.

Experienced FPGA designers understand that the performance limiter is often the data movement between memory and the DSP resources. But we can solve this "feeding-the-beast" problem by matching the rhythm of the data movement with the underlying FPGA physical architecture. Drawing from our experience with a reconfigurable compute unit for convolutional neural networks (CNNs), we present some principles to unlock latent FPGA performance. We believe that these principles are general enough to be applicable to other reconfigurable numerical applications.

Dr. Ing. Peter J. Brands (male) worked as electronic designer on the development of one of the first ultrasound colour flow mapping systems with the University of Maastricht.

Thereafter he worked on the development of ultrasound methods for tissue motion. In 1996 he got his PhD degree with a thesis focused on non-invasive methods for the assessment of wall shear rate and arterial impedance. Thereafter he started a research project on the developments of ultrasound methods for the assessment of local pulse wave velocity. In 2000, he accepted the position as research coordinator at ESAOTE.

Peter, has extensive experience with research project management, he was coordinator of several EUREKA projects, was coordinator of EU-Marie Curie project EST-514.421 and is coordinator of the ongoing FP7 FULLPHASE IP project on photoacoustic imaging. His main interests are on clinical ultrasound applications, ultrasound signal processing, ultrasound system design, Mathematics, Physics, management of research projects and the translation of research into products.

New developments in point-of-care Ultrasound functional imaging

Functional imaging, the extraction of any information regarding physical or chemical processes in tissue and their alteration through disease, is a key element for accurate and timely medical diagnosis and treatment monitoring.

Present day healthcare is under pressure due to demographic and economic challenges. The world-wide aging population and the related huge increase in chronic, age and life-style diseases will put an enormous pressure on health care costs. So, the necessary shift in healthcare delivery is focused on a reduction of hospitalisation. Accordingly, it is vital to have: point-of-care ultrasound (US) imaging systems that can provide high detailed internal structure in combination with functional classification augmenting and assisting the abilities of a general practitioner (GP). Point-of-care medical imaging systems have advanced rapidly in the recent years in regard to sensor architecture. These imaging systems must be affordable and should have high image quality and intelligent US image classification for augmenting and assisting the abilities of a GP. So, the use of point-of-care US imaging in the first line of healthcare is directly linked to the availability of programming tools for embedded multi-core computing. The next generation of US systems targeted at portable and point-of-care use will be almost fully software-based running the US application on an embedded low power computing unit. The software based point-of-care US system lead to the need of low energy multi-core computing based on System on Chip (SoC) architectures.

John Freeman loves research and innovation in the field of high performance digital design techniques. He has been working for Altera (now Intel) for the last 10 years. He started in a team responsible for developing FPGA synthesis optimizations in Quartus, then moved to the field of high level synthesis when the OpenCL research initiative began at Altera.

John previously created and managed the OpenCL Platforms team, responsible for board support packages and development of the memory, PCIe, and network interface layers of the OpenCL compiler. He is now product owner of the Intel HLS Compiler and manager in the Intel Programmable Solutions Group responsible for the high level design compiler team.

FPGA Acceleration in the Era of High Level Design

Over the past decade, FPGAs have been gaining attention as power efficient architectures for high performance compute. A significant barrier to widespread adoption of FPGAs as high performance compute engines lies in the effort required to translate complex algorithms into the detailed, low level descriptions required by traditional hardware design languages like Verilog and VHDL.

In this talk we'll explore how high level design (HLD) compilers are attempting to close the gap between traditional FPGA design techniques and the expectations coming from a new generation of FPGA designers. We will also look at some of the remaining challenges and limitations of FPGA high level design tools. The conversation will be motivated through case studies of an FPGA Deep Learning Accelerator developed using a modern HLD compiler.